file /gate_lib/readme.txt
YG, nov. 25,2000

On Michael Riepe's request, i have restored all the files
of this subdirectory. Some may remain unused anyway...

This directory contains all the logic gates necessary
to build the F-CPU's sub-units. They should be mapped
easily on any FPGA, CPLD or any fine-grained logic device.

Eache gate has a maximum of 4 inputs and counts as a
1 unit of delay. The real "speed" of the gate is a simple
scaling factor so any combination of different functions
requires more than 1 delay unit.

Beware : maj23.vhdl, maj24.vhdl and maj34.vhdl have
two gate units of latency because they use other gates.
XORs, when used alot, can also have a negative impact
on the real delay (in full-custom technologies).

The whole F-CPU design uses these gates. Some other gates
may be added in the future. One can design new architectures
that map the entities to a particular library.

To be continued...