file VHDL/EU_asu/README.TXT
YG, nov. 26,2000

This is Michael Riepe's SIMD ASU (Add/Sub Unit).
No 32-bit version is available yet but it performs
a number of 8-,16-,32- and 64-bit additions and substractions
in parallel. It can be configured for any UMAX>=64 with the
wrapper in asu.vhdl.

I have not yet tested it.
To be continued...