(C) Yann Guidon 2001 (
whygee@f-cpu.org
)
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Short introduction to the F-CPU (2)
Some features of the F-CPU Instruction Set Architecture :
32-bit instructions with 4 instruction formats only
Opcode
Flags
Op2/
Cond
Op1/
Ptr
Dest
/Op3
Format 0
(move, add, shift, load/store, cjump/call ...)
Format 1
(inc, loop ...)
Format 2
(addi, shifti, ...)
Format 3
(loadcons, geti/puti, ...)
Imm 8/16
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Instruction set census : ~110 reserved opcode values as of today, with several variations, "core" and "optional" features.
64 registers (64-bit wide in the first implementation) with R0=0
SIMD flag in most instructions allows parallel operation on registers with "undetermined" width (32, 64, 128, 256 bits ...)
Support for saturated arithmetics, IEEE Floating point, IEEE LNS and fractional integers (optional)
2r1w, 3r1w and 2r2w instructions, 3r2w register set
memory : 3 "stream hint bits" + cachability bit (7 "memory streams" are user-visible, however they are implemented)
One addressing mode only for code and data : register (post-increment possible for data)
Examples of some instructions : (the syntax orders follows the order of the binary format)
Opcode
Example
Explicitly
add
add r1,r2,r3
r3=r1+r2
load
load r1,r2,r3
r3=[r2], r2+=r1
jump
if r1=0 jump r2 link r3
if cond, r3=PC, PC=r2