f-cpu/vhdl/ready-missing.txt
created Wed Sep 12 04:41:27 2001 by whygee@f-cpu.org

missing :
---------
 a lot !

let's start with a consistent mechanism for the "configuration"
of the entity/architectures in the VHDL point of view, 
so we can select architectures according to the tool.
i have to write a few files, such as f-cpu/vhdl/configuration/simili.vhdl
and f-cpu/vhdl/configuration/vanilla.vhdl (if either tool supports
configuration files). This will allow me to cleanup the file names
and pack every architectures of a particular entity in a single file.

Currently we use scripts (batch/DOS and shell/unix), one for each tool.
It is not harmonized either.

units to design : (in order)
1) toplevel, register set, BIST, Xbar...
2) SHL, INC and SR are next. POPC is a schoolbook exercise.
3) sheduler/decoder
4) LSU/fetcher/memory interface

Michael said he's trying to do the IDU, on top of the ASU and IMU

ready :
-------

 * configuration mechanism using m4
 * ASU/IMU (ask Michael) -> i have moved the package "generic_adder.vhdl"
   in the f-cpu/vhdl/common/ directory (to avoid duplicated files).
 * some scripts for several tools (vanilla, simili, modelsim and synopsys)
   not fully tested yet, but it starts to become serious.
 * ROP2 (the testbench is not very good btw)
 * CLOCK : a "dumb" (for simulation) and a "simple" (for synthesis) architecture
   are ready, a big and "ugly" one is being done, but you wouldn't need it
   unless you do system-wide analysis (like comparing the latency with simulated
   "real" devices and timings etc).
