f-cpu/vhdl/clock/README.txt
created Mon Sep 10 00:14:23 2001 by whygee@f-cpu.org
version sam dec 29 06:16:45 2001 : YG's changes for the "stable"
 distro include renaming and moving files and entities...
 the PLL is currently disabled with this winter cleanup. 
version dim dec 30 06:01:20 2001 : added the clock period
 in the interface, two implementations are working as expected
 but not fully automated for regression tests. Vanilla and
 Simili scripts are ok.


This directory contains the description of the clock generator
for the FC0. It is still an ongoing work and it will certainly
vary a lot when "real" physical targets will be synthesised.

clock.vhdl includes a simple implementation for simulations.
It can then be adapted for synthesis. clock_powerup.vhdl
contains a more sophisticated behavioural description that
simulates the powerup sequence.

I have moved all the "ugly" and crappy PLL stuff to old_PLL/
because it doesn't work well. Borrow pieces from it at your
own risks. I will not address the PLL and clock division
issues before it is needed. When the time will come, please
respect the SR interface.

Currently i only address simulation (mainly behavioural) and
not synthesis so i only work with internal clocking, the external
clock input is not used. Before using a synthesiser, make your
own clock architecture, using the external clock and adapting
the other pins (reset and clock_ok) according to your external
clock specifications (mainly setup time). Note that when doing
an ASIC, you'll have to use existing libraries for your target
technology. PLLs come in much more tested form with analog
features. In the future, it would be cool to have a small
collection of generic clock drivers.


have fun,
YG
