f-cpu/vhdl/eu_rop2/README.txt
created Thu Aug 23 01:10:22 2001 by whygee@f-cpu.org

this is a newer version of the ROP2 unit.
it is more up to date than the version released 1 year ago
and it comprises the COMBINE and MUX operation modes.

The unit is now split into 2 files, each acting at a separate
level in the pipeline. The usual part is done as always, after
the Xbar level. It performs the operations.
The other part is a pure control signal stuff : the operation
function is decoded (3->4 bits) and amplified (the fanout
would be four time 1 to 64 bits in the ROP2 unit itelf).
Now the four function signals amplified 16x and the last
stage (4x fanout) is done after the stage flip-flops.
i guess that 4x is a reasonable fanout, at least much more
acceptable than the previous version :-)

The flip flops are implemented outside of the design,
in the top level file (not available yet).


Sat Sep  1 05:57:32 2001 :

Note : an even better version would take other fanout problems
into account (the 8-fanout of the combine functions and
the 1->64 fanout for the MUX control signal). Currently,
i let the synthesiser manage that itself (i solved the most
critical part) but the VHDL could be modified a bit if it is
still too tight. After all, even a 10% clock cycle boost is
interesting.

The enclosed PS file shows what the VHDL does. Some fanout
problems are shown and solved, but they are not all integrated
in the VHDL files. I have also tried to "compile" the LUT
by hand, but it is just a silly exercise : the LUT will not
be synthesised like that in a real design. It just gives you
a rough estimation of its complexity when no complex logic
minimization is performed.


ven dec 14 01:21:52 GMT 2001 :
I hope that this one is the final version :-)
the fanout problem should be over. the files serve as
example in a french article for Linux Magazine France.
I slowly integrate the newest files and i should start
using Cadence now...


Tue Jun 25 19:41:53 CEST 2002

Note : combines of more than 8 bits is difficult
if we want to keep the operating stage small.
16-bit is still possible but not done. 32- and 64-bits
combine would probably use another pipe stage, which
is not wanted at all. In case it is required, then
use the ASU in saturated mode.


Sun Jul  7 00:37:32 CEST 2002

Starting to apply MR's recommendations and VHDL coding
guidelines (more functions, less signal assignments,
'87 style instanciations)

Tue Jul 23 05:28:02 CEST 2002

Trying to add stimulib.
