f-cpu/vhdl/eu_bist/README.txt
created Sat Jun 29 10:03:57 CEST 2002 by whygee@f-cpu.org

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Note that this EU is needed in ASICs, not in FPGAs where the
silicon is meant to be fault-free. The presence of this unit
is thus determined by the user in the high-level configuration
files. However the capacity to clear the register set and
other registers will be lost.
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The BIST unit is not an "Execution Unit" but it is convenient
to treat it as if it was one.

It is in charge of checking the core's guts before starting
to execute some code. It will check and initialise/reset all the
EUs and the register set. The fact that it is treated as an EU
makes it easy to "plug" it in the pipeline, so it can send
and receive data to all other units.

As you must already know, the allowed critical datapath is
extremely short in F-CPU. It would not be a good solution to
use the classical BIST solutions that use specific pipeline
stages integrating LFSRs etc., or the operating frequency
would be significantly impacted.

The solution is to create a "fake" EU that sends data to
the other EUs and checks the outputs. A "signature" is
created like in other techniques, but the whole process is
pipelined and we try to reuse existing EUs to perform some
of the operations. Several EUs are chained too, since the
goal is to know whethere there is a fault, not to know where.

* Since it is run after power-up, its purpose is first to
"clear" the pipeline stages from the unknown states.
So it runs a series of operations without caring for the
results. This inserts known data in the pipes so everybody
is happy.

* Then is tests and clears the register bank. In fact, it
uses a "logarithmic" technique which is designed to end with
zeroes all over the bank, so there is no explicit "clear"
operation and no reset signal in the bank.

* It also exploits the vectors that are sent to the Xbar
and they are used to test the EUs in parallel. The result
is also reused ("chained") to other EUs in order to test
as many wires and units as possible.

* POPC is used to "compact" the signature that is read
from the Xbar and which feeds the internal LFSR.
This LFSR is tested at the end of the test period and
the CPU can start booting when the result is satifying.

The expected length of the BIST function is a several
tens of thousands of cycles.

The other side of this unit is that it must control other
signals and bypass or override the scheduler and other
things. It's not always very clean but it must not be too
intrusive in the pipeline, at the cost of some complexity
and latency.

The whole BIST system contains the pipe stage (with a vector
generator and a MISR+comparator) and a scheduler/controller
that sends the right signal at the right moment.
The MISR is not difficult but the vector generator can't
be a simple LFSR (or even take the MISR's value as is)
because logarithmic tests require a different kind of
signals.

However, the BIST unit has several inputs and outputs
so all Xar buses (3r2w) are tested, and the MISR can also
read and write on the Xbar. Because of the compaction,
the MISR must be located close to the POPCOUNT unit's
output.
