/yg/f/f-cpu/c/eu_rop2/README.txt
created Sat Jul 20 21:30:09 CEST 2002 by whygee@f-cpu.org

This is the first unit that was written for this simulator.
It is mainly maintained by YG.

 - beware to not switch ROP_in_A and ROP_in_B inadvertantly
 - same for MUX : the inputs are probably swapped.
 - the testbench is not finished. In fact, i'm waiting
   for a little library that provides stimuli so the
   C and VHDL will be tested in parallel.
 
