f-cpu/vhdl/clock/README.txt
created Mon Sep 10 00:14:23 2001 by whygee@f-cpu.org

This directory contains the description of the clock generator
for the FC0. It is still an ongoing work and it will certainly
vary a lot when "real" physical targets will be synthesised.

clock.vhdl proposes a 'swiss army chainsaw' version for the
unit in the "ugly" architecture. I failed to generate a PLL
but at least i have written some code for generating a clock
and its subfrequencies based on internal or external sources.

clock_vanilla.vhdl is a stripped-down version for the compilers
that do not understand the furiously insane code in the previous
file. Vanilla is one example of such compilers.

Synthesisers have to use the "simple" architecture in
clock.vhdl, because it is the most basic thing that is necessary
when starting to make a chip. If you want more sophisticated stuff,
just borrow it from the "ugly" architecture in the same file.

clock.obj and clock.ps give a shecmatic overview of the circuit
(currently incomplete because the PLL is not working). The .obj
is the source file for tgif which has generated the .ps file.

clock_testbench.vhdl serves to check if the unit works.
It may not be fully functional or useful, depending on the
desired features to be tested...

note that when doing an ASIC, you'll have to use existing
libraries for your target technology. PLLs come in much
more tested form with analog features.

You can read more about the internals in HowItWorks.txt.

have fun,
YG
