f-cpu/vhdl/clock/HowItWorks.txt
created Mon Sep 10 03:18:20 2001 by whygee@f-cpu.org

(this file has not been updated to reflect the changes, sorry)

This file explains some dumb stuff about the ugly PLL
designed in this unit.

VHDL for digital circuits is very limited. I had to "cheat"
a lot and remember some stuffs that i have learnt at
school (ouch !). This proves that school is not a bad thing
after all.

The NCO loop is adapted from a "digital" (pseudo) signal
generator we did at school. Except that here, we can't
play with the R/C constants :-( so i had to use something
else : a line of (delaying) inverters. The output of every two
inverters is selected and if each inverter delays t time, we can
do frequencies at 1/(2n+m t). Of course we have to
be careful because m must be odd and have at least several
gates. For a "direct" use, m should be at least 4*6
because the logic layers have 6 logic gates of CDP
plus the setup+hold time for the pipeline gates.
Considering that the logic state of these gates change
once per cycle, and that the logic gates are more complex
than inverters, the number of 6 layers must be increased
(at least doubled) but OTOH the state of the inverters change
2* per cycle.

I think that this NCO can work in real applications
but it is more intended to "model" real HW rather
than implementation. I tried to be careful about power
consumption issues and particularly about the clocking.
In a simulator, this can have the effect of reducing the
number of "events" and thus speed up the simulations,
but this is not garanteed.

I want to make a "scalable" "configurable" design and
i could write a configurable multiplexor for the loop,
so i used a dirty linear trick. I did not find any other
"clean" solution than doing a "for generate" with a
simple "brick" containing a pair of inverters and the
selection for this signal. if you know a better way,
please tell me !


The clock dividers are designed to work
both as direct clock dividers or inside a PLL. The clock
signal output is the MSB of each N-bit counter. The counter is
"incremented" with a number from 1 to 2^N (with a N+1 bit adder).
The result is latched by every rising edge of the input.
The maximum generated clock frequency is thus freq_in/2 and
the minimum speed is freq_in/(2^(N+1)). This way, if you have
a 4-bit counter, you can generate internal frequencies such
as 15:4 for example, when you have a 133MHz front-end with
an internal speed of 500MHz. 
However if you have no PLL you are more limited with the available
clock ratio ranges : you have to input either the correct frequency
in the chip or a much higher frequency so it can be divided by
at least two. I don't know any design that can "do" a counter
updated on both rising and falling edge of the clock.

The idea i have in mind for doing the PLL in VHDL is that
the "phase" can be seen as the difference between the two
counters. I thought about using a substractor between the two
"prescalers" but it creates problems about the timing
(when should the ouput be sampled ?).

The other (and better) idea is that the two MSB feed a second
set of counters (base-2 this time). When the internal counter
reaches the maximum count, we check if the other counter (external
divided clock) has overflowed. if yes, we increment the internal
generator frequency, or we decrement it otherwise.
It should be rather easy...
The "response time" for the PLL will then be determined by the
depth of these counters. More depth means more stability but
the logic could not be fast enough (unless you use a pile of
JK gates in series). Let's try with 4 bits...

Oh yes, this means that the internal generator's frequency is controlled
by an up/down counter, with a mux at the output to select with
the user frequency (not shown in the PS file either).

But this is worthless because you better use an existing PLL.
Unless you want to simulate a "real" system with all the timings.
But be very careful : the PLL stability is not very good !!!!!
