/yg/f/f-cpu/c/eu_rop2/README.txt
created Sat Jul 20 21:30:09 CEST 2002 by whygee@f-cpu.org

This is the first unit that was written for this simulator.
It is mainly maintained by YG.

 - beware to not switch ROP_in_A and ROP_in_B inadvertantly
 - same for MUX : the inputs are probably swapped.
 - the testbench is not finished. In fact, i'm waiting
   for a little library that provides stimuli so the
   C and VHDL will be tested in parallel.
 
Updated Sat Jul 27 03:32:43 CEST 2002

* The VHDL test vector generator is created and it's much
more flexible => vect_rop2.c is moved to deprecated

* the pipeline is now enabled and tested.

==> this unit seems to be nicely OK.

BUT i have moved the dump function to eu_rop2.c,
so it is factored, it is used by both fcpusim and
test_rop2.c. I wish the same is done for the other
units.
