F-CPU instruction set
=====================

Rev. 0.0.1 - 08 September 1998

Please revise this as often as needed.

Instruction notation
--------------------

We'll use standard gas (GNU Assembler) notation whenever possible. This is basically AT&T assembler notation.

(provide reference documents on the Web describing this notation).

Memory addressing
-----------------

The F-CPU architecture recognizes byte-addressable memory with a 64-bit address range, in the same endianness as the x86
architecture i.e. little endian mode.

I/O has the same address space as the x86 architecture i.e. 16 bits

Operands
--------

All operands are memory locations or immediate data (16 bits only), since we don't have (from a software point of view) registers.
The only exceptions are the PC (program counter) and the ST (status or flags register). The PC is a 64-bit register. The ST can be
either a 32-bit register (because I don't think we'll need more than 32 flags/status bits) or a 64-bit register for consistency; I
favour the latter, even if we have lots of unused bits.

All operands can be defined as either byte (8 bits), word (16 bits), dword or double (32 bits) or qword or quad (64 bits).
Unaligned operands that span two registers (two 8 byte regions) are allowed, but will probably cause a pipeline stall. The
compiler/assembler should ensure all operands are aligned for maximum performance.

Instruction classes
-------------------

We'll use the following broad instruction classes defined by H&P for the DLX architecture:

1) Moves (H&P defines this as load/store instructions).
2) ALU operations.
3) Branches and Jumps.
4) Floating Point.

We'll add a fifth class for special instructions e.g. hlt (halt), so:

5) Special.

Let's see which instructions we have in each class.

I - Moves
---------

Two basic types of moves:

a) Memory-to-memory. The compiler/assembler must encode this in the shortest possible format.

b) Memory-to-I/O.

II - ALU operations
-------------------

That is pretty classic.

a) Arithmetic

        add

        subtract

        negate

        increment

        decrement

        compare

        multiply

        divide

b) Logical

        and

        or

        xor

        not

        shift

        rotate

III - Branches and Jumps
----------------------


IV - Floating Point Instructions
-------------------------------

Floating Point instructions are always decoded to generate an exception. They
will also either activate the (external) FPU if one is present or, if no FPU exists in the system, start software emulation of FP
arithmetic.


V - Special instructions
------------------------

1) hlt : Halt. Standard halt behaviour. Must power down the CPU as much as possible.

2) sti : Enable interrupts.

3) cli : Disable interrupts.
