1. The name of the chip, product or technology

the F-CPU Instruction Set Architecture and the F-CPU Core #0 ("FC0")


2. General features of the chip, product or technology

* Fully parameterizable VHDL'93 source code distributed under GPL
  and F-CPU Charter.
* retargetable to a broad range of technologies
* SIMD, "undetermined register size" (32, 64, 128, 256 ...)
* 64 registers (64-bit wide in the first implementation)
* 32-bit instructions with 4 instruction formats only
* superpipelined (very short matched pipeline stages)
* 1 instruction per cycle issued In-Order
   and Out Of Order Completion (for the FC0)
* Execution pipeline freed from exceptions (no rollback possible)
* Zero-delay branch instruction (in the ideal case)
* Smooth Register Back ("SRB") mechanism lowers context switch time


3. Specific features that will be discussed in detail at
   Embedded Processor Forum

* instruction scheduling
* memory interface

4. Whether the chip will be formally announced or
   disclosed for the first time at Embedded Processor
   Forum (if not, what prior disclosures or announcements
   are planned)

It is the first public presentation in a congress in the US.
The F-CPU team was presented during two conferences in Berlin
(17C3 : http://www.ccc.de/congress/fahrplan/event/153.en.html
 16C3 : http://www.ccc.de/events/congress99/doku/fcpu.html)
but there was only a short technical introduction, while
some key details (see 3.) will be discussed.

5. For non-chip announcements, please provide details
   on the product to be announced, its relevance to the
   event, and particulars that will help evaluate the
   presentation

Today, the F-CPU is the only configurable SIMD 64-bit
general-purpose RISC core aimed at high performance
applications (multimedia or scientific computations).
It is a very recent design (1999) originally meant to
provide a free, ununcumbered alternative to the Merced.

Contrarily to the LEON, the F-CPU defines a new instruction
set and is designed to last much longer. It is "by design"
extensible and scalable in several ways, providing forward
and backward compatibility for several decades. The first
core (FC0) could be used as replacement for the aging MIPS,
SPARC, ALPHA...

Contrarily to the ARC Cores and similar "configurable cores"
offers, the F-CPU is not a "black box" but a completely
transparent design that allows complete visibility to the
engineer. The F-CPU is based around a clean ISA and some simple
scheduling rules, leaving a lot of freedom to the implementor.


6. Other descriptive information about the presentation

{not defined yet. maybe a free distribution of CDROMs}

7. Company name

It is a community development on the Internet, not a company "product".

8. Speaker's name (should be the chief architect or lead
   designer of the product)

Yann Guidon

9. Speaker's job title

Software development Engineer at Mentor Graphics (that's how i
earn my life), main F-CPU contributor.

10. Speaker's biography (30 words or less)

Joined the F-CPU Design Team on the Internet in Dec. 1998,
influenced the design when the F-CPU ISA became RISC and
defined the FC0 in mid-1999, Mentor Graphics employee
since nov. 2000.

11. Speaker's address, phone, fax, email address and
    administrator (if any)

email : whygee@f... (personal) and yann_guidon@m... (job)
snail mail address :
 Yann Guidon
 13 rue Francois Couperin
 93110 Rosny sous bois
 France
phone : +33 1 64 86 62 07 (business)


12. Abstract title

proposed title :
Instruction scheduling and the memory interface of the F-CPU Core #0


13. P.R. or Marcom contact (include phone, fax, and email)

no marketing. see http://www.f-cpu.org or email me.

14. Your abstract or outline should not exceed 1000 words.

