Pin Description Overview
|
Peripheral Interface Bus
|
| FBus[0:63] |
in/out |
64-bit data/address bus. operates either in 1
address + 8 data cycle bursts, and multiples thereof, or in 1 address +
1 data cycle mode. |
64 |
| FBusReq# |
out |
Request for bus from F-Southbridge |
1 |
| FBusGnt# |
in |
Grant of bus to F-Southbridge |
1 |
| Total of 66 pins. |
| PCI Bus Pins |
| PciAD[0:31] |
in/out |
PCI Address/Data Bus. |
32 |
| PciPar |
in/out |
PCI Parity Indicator. |
1 |
| PciReq[0:7] |
in |
PCI Bus Request Signals. |
8 |
| PciGnt[0:7] |
out |
PCI Bus Grant Signals. |
8 |
| PciClk |
out |
PCI Clock Signal. |
1 |
| PciC/BE[0:3] |
t/s |
PCI Command/Byte Enable Bus. |
4 |
| PciReset# |
out |
PCI Reset Signal. |
1 |
| PciFrame# |
s/t/s |
PCI Cycle Frame Signal. |
1 |
| PciTRdy# |
s/t/s |
PCI Target Ready Signal. |
1 |
| PciIRdy# |
s/t/s |
PCI Initiator Ready Signal. |
1 |
| PciStop# |
s/t/s |
PCI Transaction Stop Signal. |
1 |
| PciLock# |
s/t/s |
PCI Bus Lock Signal. |
1 |
| PciIDSel[0:7] |
out |
PCI Initialization Device Select Signals. |
8 |
| PciDevSel# |
s/t/s |
PCI Device Select Signal. |
1 |
| PciPErr# |
in |
PCI Parity Error Signal. |
1 |
| PciSErr# |
in |
PCI System Error Signal. |
1 |
| PciSBO# |
in/out |
PCI Snoop Back Off Signal. |
1 |
| PciSDONE |
in/out |
PCI Snoop Done Signal. |
1 |
| PciAD[32:63] |
in/out |
PCI Address/Data Bus for 64-bit PCI Extension. |
32 |
| PciC/BE[4:7] |
in/out |
PCI Command/Byte Enable Bus for 64-bit PCI Extension. |
4 |
| PciReq64# |
in/out |
PCI Request 64-bit Transfer Signal for 64-bit
PCI Extension. |
1 |
| PciAck64# |
in/out |
PCI Acknowledge 64-bit Transfer Signal for 64-bit
PCI Extension. |
1 |
| PciPar64 |
in/out |
PCI Parity Indicator for 64-bit PCI Extension. |
1 |
| INTA# - INTD# are connected to the Programmable
Interrupt Controller. |
4 |
All pins operate as per PCI Specification 2.1.
Total of 107 pins. |
| AGP Bus Pins |
| AgpAD[0:31] |
in/out |
AGP Address/Data Bus. |
32 |
| AgpPar |
in/out |
AGP Parity Indicator. |
1 |
| AgpReq |
in |
AGP Bus Request Signal. |
1 |
| AgpGnt |
out |
AGP Bus Grant Signal. |
1 |
| AgpClk |
out |
AGP Clock Signal. |
1 |
| AgpC/BE[0:3] |
t/s |
AGP Command/Byte Enable Bus. |
4 |
| AgpReset# |
out |
AGP Reset Signal. |
1 |
| AgpFrame# |
s/t/s |
AGP Cycle Frame Signal. |
1 |
| AgpTRdy# |
s/t/s |
AGP Target Ready Signal. |
1 |
| AgpIRdy# |
s/t/s |
AGP Initiator Ready Signal. |
1 |
| AgpStop# |
s/t/s |
AGP Transaction Stop Signal. |
1 |
| AgpLock# |
s/t/s |
AGP Bus Lock Signal. |
1 |
| AgpIDSel |
out |
AGP Initialization Device Select Signal. |
1 |
| AgpPErr# |
in |
AGP Parity Error Signal. |
1 |
| AgpSErr# |
in |
AGP System Error Signal. |
1 |
| AgpSBO# |
in/out |
AGP Snoop Back Off Signal. |
1 |
| AgpSDone |
in/out |
AGP Snoop Done Signal. |
1 |
| AgpPipe# |
s/t/s (in) |
AGP Pipelined Request Signal. |
1 |
| AgpSBA[0:7] |
in |
AGP SideBand Address Signals. |
8 |
| AgpRBF# |
in |
AGP Read Buffer Full Signal. |
1 |
| AgpWBF# |
in |
AGP Write Buffer Full Signal. |
1 |
| AgpST[0:2] |
out |
AGP Status Bus. |
3 |
| AgpAD_STB0 |
s/t/s (in/out) |
AGP Differential AD Bus Strobe 0. |
1 |
| AgpAD_STB0# |
s/t/s (in/out) |
AGP Differential AD Bus Strobe 0. |
1 |
| AgpAD_STB1 |
s/t/s (in/out) |
AGP Differential AD Bus Strobe 1. |
1 |
| AgpAD_STB1# |
s/t/s (in/out) |
AGP Differential AD Bus Strobe 1. |
1 |
| AGPTypeDet |
in |
AGP Type Detect. |
1 |
All pins operate as per AGP Specification 2.0.
Total of 69 pins. |
| Miscellaneous Pins |
| Reset# |
in |
F-Corelogic Reset Signal. F-Corelogic exits reset
state on the rising edge of Reset# |
1 |
| VCC |
|
F-Corelogic Power. 1.5V? 3V? 5V? |
? |
| GND |
|
F-Corelogic Ground. |
? |
Grand total of 243+? pins.