F-CPU Design Team
FCPU MANUAL REV. 0.2

 

            Appendix B :

 

 

 

The F-CPU Opcode
map overview

 

 

 

 

 

 
Summary

            This document is a first census of the available instructions. It is currently used to determine the efficiency of the instruction word format as well as the structure of the needed decoding logic.

 

Legend :

Core :there is an asterisk if implementating this instruction is mandatory.
F0 :this instruction will be implemented in the F0 chips.
Form :what ressources/fields are used at decode time.
SIMD :if the instruction uses the SIMD flag in the opcode.
EU :Execution Unit that the instruction uses.
1C :one register is used as a condition and its value is not used as such.
(P) :one register is a pointer.
(I) :one register is used as a pointer to instructions.
(t0) :test if register operand is zero.
(t0-> T) :trap if register operand is zero.
3r :read three registers.
2r :read two registers.
1r :read one register.
i8 :8-bit immediate.
i16 :16-bit immediate.
1w :write one register.
(tMSB) :test is MSB (bit sign) is set.
! :SIMD has no meaning here (it is implicit or irrevelant).

 

Preliminary opcode map overview :

#major
opcode		names and
mnemonics		C
o
r
e		F
0		FormS
I
M
D		EUremarks
1OP_ADDadd, adds, addu**(t0) 2r1w*ASU1 bit left for LNS or
fractional (Q) format
2OP_ADDaddc *(t0) 2r2w*ASU(idem, LNS/Q)

 

 

mar avr 25 04 : 14 : 55 CEST 2000 by Whygee
Copyright (c) 1999-2000 The F-CPU Group Design Team.

not yet done :

3OP_ADDIaddi *i81r1w*ASU(idem, LNS/Q)4OP_ADDSUBaddsub, addsubs  (t0) 2r2w*ASU (x2)(idem, LNS/Q)5OP_SUBsub, subb**(t0) 2r1w*ASU(idem, LNS/Q)6individual opcode ?subb *(t0) 2r2w*ASU(idem, LNS/Q)7OP_SUBIsubi *i81r1w*ASU(idem, LNS/Q)8OP_MULmul, muls**(t0) 2r1w*IMU(idem, LNS/Q)9individual opcode ?mulh, mulsh  (t0) 2r2w*IMU(idem, LNS/Q)10OP_MULImuli *i8r1w*IMU(idem, LNS/Q)11OP_MACmac, macs  (t0) 3r1w*IMU+ASU(idem, LNS/Q)12individual opcode ?mach, macsh  (t0) 3r1w*IMU+ASU(idem, LNS/Q)13OP_DIVdiv, divs**(t0-> T) 2r1w*IDU(idem, LNS/Q)14individual opcode ?divm, divms  (t0-> T) 2r2w*IDU(idem, LNS/Q)15OP_DIVIdivi *i81r1w*IDU(idem, LNS/Q)16OP_MODmod, mods  (t0-> T) 2r1w*IDU(idem, LNS/Q)17OP_MODImodi  i81r1w*IDU(idem, LNS/Q)18OP_POPCOUNTpopcount  (t0) 2r1w*? 18-2OP_POPCOUNTIpopcounti  (t0) i81r1w*? 19OP_INCinc *1r1w*INC 20OP_DECdec *1r1w*INC 21OP_NEGneg *1r1w*INC 22OP_ABSabs *(tMSB) 1r1w*INC 23OP_SCANscan, lsb1, lsb0,
msb1, msb0  (t?) 1r1w*INC 24OP_CMPLcmpl  2r1w*INC 25OP_CMPLIcmpli  i81r1w*INC 26OP_CMPLEcmple  1r1w*INC 27OP_CMPLEIcmplei  i81r1w*INC 28OP_MAXmax  2r1w*INC 29OP_MAXImaxi  i81r1w*INC 30OP_MINmin  2r1w*INC 31OP_MINImini  i81r1w*INC 32OP_SORTsort  2r2w*INC 33OP_LADDladd  2r1w*LASU 34OP_LSUBlsub  2r1w*LASU 35OP_L2INTl2int  (tMSB) 1r1w*LCONV 36OP_INT2Lint2l  (t0) 1r1w*LCONV 37OP_SHIFTLshiftl**2r1w*SHUFFLER1 bit left for LNS ?38OP_SHIFTLIshiftli *i81r1w*SHUFFLER(idem, LNS)39OP_SHIFTRshiftr**2r1w*SHUFFLER(idem, LNS)40OP_SHIFTRIshiftri *i81r1w*SHUFFLER(idem, LNS)41OP_SHIFTRAshiftra**2r1w*SHUFFLER(idem, LNS)42OP_SHIFTRAIshiftrai *i81r1w*SHUFFLER(idem, LNS)43OP_ROTLrotl**2r1w*SHUFFLER 44OP_ROTLIrotli *i81r1w*SHUFFLER 45OP_ROTRrotr**2r1w*SHUFFLER 46OP_ROTRIrotri *i81r1w*SHUFFLER 47OP_BITOPbitop, bchg, bset,
bclr, btst  2r1w*SHUFFLER 48OP_BITOPIbitopi, bchgi, bseti,
bclri, btsti  i81r1w*SHUFFLER 49OP_BITREVbitrev  2r1w SHUFFLER 50individual opcode ?bitrevo  3r1w SHUFFLER 51OP_BITREVIbitrevi  i81r1w SHUFFLER 52individual opcode ?bitrevio  i82r1w SHUFFLER 53OP_BYTEREVbyterev *(t0) 1r1w*SHUFFLER 54OP_MIXmixl, mixh *(t0) 1r1w!SHUFFLER 55OP_EXPANDexpandl, expandh *(t0) 1r1w!SHUFFLER 56OP_SDUPsdup *2r1w!SHUFFLER 56OP_SDUPIsdupi *i81r1w!SHUFFLER 57OP_LOGIClogic, or, orn, and,
andn, xor, nxor,
not, nor, nand**2r1w!ROP2 58OP_LOGICIlogici, andi,
andni, ori, xori  i81r1w ROP2not enough
room here.59OP_FADDfadd, faddxf1 2r1w*FASU 60OP_FSUBfsub, fsubxf1 2r1w*FASU 61OP_FMULfmul, fmulxf1 2r1w*FMU 62OP_F2INTf2int, f2intxf1 1r1w*? 63OP_INT2Fint2f, int2fxf1 1r1w*? 64OP_FIAPRXfiaprx, fiaprxxf1 1r1w*FLUT 65OP_FSQRTIAPRXfsqrtiaprx,
fsqrtiaprxxf1 1r1w*FLUT 66OP_FDIVfdiv, fdivxf2 2r1w*? 67OP_FSQRTfsqrt, fsqrtxf2 1r1w*? 68OP_FLOGflog, flogxf3 1r1w*? 69OP_FEXPfexp, fexpxf3 1r1w*? 70OP_FMACfmac, fmacxf3 3r1w*FASU+FMU 71OP_FADDSUBfaddsub, faddsubxf3 1r1w*FASU x2 72OP_LOADload, loade**(P) (t0) 1r1w LSU 73*load, loade *(P) (t0) 2r2w LSU+ASU 74OP_LOADIloadi, loadie *(P) [t0]i81r2w LSU+ASU 75OP_LOADFloadf, loadfe *(P) (t0) 2r2w LSU+ASU 76OP_LOADIFloadif, loadife *(P) [t0]i81r2w LSU+ASU 77OP_STOREstore, storee**(P) (t0) 2r LSU 78*store, storee *(P) (t0) 3r1w LSU+ASU 79OP_STOREIstorei, storeie *(P) (t0) i82r1w LSU+ASU 80OP_STOREFstoref, storefe *(P) (t0) 3r1w LSU+ASU 81OP_STOREIFstoreif, storeife *(P) (t0) i82r1w LSU+ASU 82OP_CACHEMMcachemm  (P,t0) 2r ? 83OP_MOVEmove -n, -s**1C1r1w  #define OP_MOVE 084OP_LOADCONSloadcons**i161w  2 or 4 opcodes (range)85OP_LOADCONSXloadconsx**i161w  2 or 4 opcodes (range)86OP_GETget**1r1w SR 87OP_GETIgeti *i161w SR 88OP_PUTput**2r SR 89OP_PUTIputi *i161r SR 90OP_LOADMloadm  (P,t0) 3r  immediate
version needed...91OP_STOREMstorem  (P,t0) 3r  (idem, immediate)92OP_JMPAjmpa**h, (P) 1C1r1w  missing : hints...93OP_LOADADDRloadaddr,
loadaddrd,
loopentry**(t0) 1r1w ASU 94OP_LOADADDRIloadaddri,
loadaddrid**i161w ASU 95OP_LOOPloop**(I) 2[1]r1w ASU/INC 96OP_SYSCALLsyscall, trap**i161r   97OP_HALThalt**    98OP_RFErfe**    99OP_SRB_SAVEsrb_save      100OP_SRB_RESTOREsrb_restore      102OP_SERIALIZEserialize      

 

 

part5.html feb. 27th, 2000 by Whygee