Symphony EDA (R) VHDL Compiler/Simulator Module VhdlE, Version 1.4, Build#32.
Copyright(C) Symphony EDA 1997-2000. All rights reserved.
Reading d:\vhdl\simili\bin\symphony.ini ...
Library 'ieee'		==> $SYMPHONY/Lib/Ieee/Ieee.sym
Library 'work'		==> work.sym
Reading  work.sym\rop2_testbench\rop2_testbench.var
Reading  work.sym\eu_rop2\eu_rop2.var
Reading  work.sym\fcpu_config\fcpu_config(body).var
Reading  $SYMPHONY\Lib\Ieee\Ieee.sym\std_logic_1164\std_logic_1164(body).var
Reading  $SYMPHONY\Lib\Ieee\Ieee.sym\numeric_std\numeric_std(body).var
Reading  $SYMPHONY\Lib\Ieee\Ieee.sym\std_logic_textio\std_logic_textio(body).var
Reading  work.sym\rop2_testbench\rop2_testbench(test).var
Reading  work.sym\eu_rop2\eu_rop2(arch1).var
	# of Signals       = 609
	# of Components    = 1
	# of Processes     = 84
	# of Drivers       = 392
Design Load/Elaboration Elapsed Time: 00h:00m:03s:063ms
*** decoding line #1
* cycle # : 1   ROP2 function:0
 Din_A=0000000000000011
 Din_B=0000000000000101
  Dout=0000000000000001
*** decoding line #2
* cycle # : 2   ROP2 function:1
 Din_A=0000000000000011
 Din_B=0000000000000101
  Dout=0000000000000010
*** decoding line #3
* cycle # : 3   ROP2 function:2
 Din_A=0000000000000011
 Din_B=0000000000000101
  Dout=0000000000000110
*** decoding line #4
* cycle # : 4   ROP2 function:3
 Din_A=0000000000000011
 Din_B=0000000000000101
  Dout=0000000000000111
*** decoding line #5
* cycle # : 5   ROP2 function:4
 Din_A=0000000000000011
 Din_B=0000000000000101
  Dout=FFFFFFFFFFFFFEEE
*** decoding line #6
* cycle # : 6   ROP2 function:5
 Din_A=0000000000000011
 Din_B=0000000000000101
  Dout=FFFFFFFFFFFFFEEF
*** decoding line #7
* cycle # : 7   ROP2 function:6
 Din_A=0000000000000011
 Din_B=0000000000000101
  Dout=FFFFFFFFFFFFFFEF
*** decoding line #8
* cycle # : 8   ROP2 function:7
 Din_A=0000000000000011
 Din_B=0000000000000101
  Dout=FFFFFFFFFFFFFFFE
*** decoding line #9

   ### End of vector file ###.

Simulation stopped at: 80 ns
Simulation Elapsed Time: 00h:00m:00s:042ms
